Heretofore, TTL logic used to be the main type of general-purpose logic. However, in the recent years, CMOS logic has replaced the TTL logic as the main type.
The types of CMOS logic include standard CMOS logic (with a chip size about 20 mm and a transmission delay time about 80 nsec), high-speed CMOS logic (with the same chip size as above, and a transmission delay time about 15 nsec), new high-speed CMOS logic (with the same chip size and a transmission delay time about 8 nsec), and advanced high-speed CMOS logic (with the same chip size and a transmission delay time about 4 nsec).
In a conventional LSI chip, such as a CMOS circuit providing a signal transmission circuit, inverters may be used as a driver circuit and a receiver circuit.
FIGS. 10-13 show some examples of a conventional signal transmission circuit.
In the circuit shown in FIG. 10, driver circuit 50 using inverter 52 and receiver circuit 51 using inverter 53 are connected to each other by wiring 200, and the signal is transmitted from driver circuit 50 to receiver circuit 51 by wiring 200, so that the so-called rounding of the signal can be reduced.
In the circuits shown in FIGS. 11-13, in the case when the signal transmission time becomes longer as the signal transmission distance is increased so that the time constant RC due to parasitic resistance and capacitance of wiring 200, corresponding to the delay in the signal transmission time, inverter 54 (FIG. 11), inverters 55, 56 (FIG. 12), or inverters 57-59 (FIG. 13) are connected in series between driver circuit 50 and receiver circuit 51 to improve the delay of the signal transmission time. These inverters 54-59 act as an intermediate amplifier circuit, respectively.
FIG. 14 shows a diagram of characteristics illustrating the relationship between the power consumption of the conventional signal transmission circuit and the wiring length shown in FIGS. 10-13.
In this figure, curve OC in the case when no inverter is used as the intermediate amplifier circuit (the graph which shows the characteristics of the signal transmission circuit in FIG. 10) indicates that the power consumption is about 1.05 mW for a wiring length of 20.times.1000 .mu.m (2 cm) in an LSI chip. In this case, the signal cycle time is 60 nsec, the wiring capacitance is 0.25 FF/1 .mu.m, and there is a wiring resistance of 0.1 .OMEGA./square.
Curve 2C in the case when inverter 54 is used as the intermediate amplifier circuit (the graph illustrating the characteristics of the signal transmission circuit of FIG. 11) indicates that the power consumption is about 1.1 mW for a wiring length of 20.times.1000 .mu.m. Curve 3C in the case when inverters 55, 56 are used as the intermediate amplifier circuit (the graph illustrating the characteristics of the signal transmission circuit of FIG. 12) indicates that the power consumption is about 1.15 mW for a wiring length of 20.times.1000 .mu.m. Curve 4C in the case when inverters 57-59 are used as the intermediate amplifier circuit (the graph illustrating the characteristics of the signal transmission circuit of FIG. 13) indicates that the power consumption is about 1.2 mW for a wiring length of 20.times.1000 .mu.m.
That is, in the conventional signal transmission circuit, when the wiring length is kept constant such as 2 cm, as more inverters 54-59 are connected in series as intermediate amplifiers interposed in the wiring 200 (FIGS. 10-13), the power consumption of the signal transmission circuit increases. When the signal transmission circuit without an inverter used as an intermediate amplifier as shown in FIG. 10 is compared with the signal transmission circuit shown in FIG. 13 with three inverters that are used as intermediate amplifiers, it can be seen that while the power consumption of the signal transmission circuit in FIG. 10 is 1.05 mW, for the signal transmission circuit shown in FIG. 13, the power consumption is increased to 1.2 mW.
FIG. 15 shows the relationship between the wiring length and the delay in signal transmission. FIGS. 10-13 show the simulation results.
In FIG. 15, the ordinate represents the delay, while the abscissa represents the wiring length.
For example, when the wiring length within LSI chip is 20.times.1000 .mu.m (2 cm), curve OC in the case when no inverter is used as the intermediate amplifier circuit (the graph which shows the characteristics of the signal transmission circuit in FIG. 10) indicates a delay of about 5.5 nsec; curve 2C in the case when inverter 54 is used as the intermediate amplifier circuit (the graph illustrating the characteristics of the signal transmission circuit of FIG. 11) indicates a delay of about 5 nsec; curve 3C in the case when inverters 55, 56 are used as the intermediate amplifier circuit (the graph illustrating the characteristics of the signal transmission circuit of FIG. 12) and curve 4C in the case when inverters 57-59 are used as the intermediate amplifier circuit (the graph illustrating the characteristics of the signal transmission circuit of FIG. 13) indicate a delay of about 4.5 nsec.
That is, in the conventional signal transmission circuit, when the wiring length is kept constant at 2 cm, as more inverters 54-59 are connected in series as intermediate amplifiers interposed in the wiring 200 (FIGS. 10-13), the delay time becomes shorter. When the signal transmission circuit without an inverter used as an intermediate amplifier as shown in FIG. 10 is compared with the signal transmission circuit shown in FIG. 13 with three inverters that are used as intermediate amplifiers, it can be seen that while the delay of the signal transmission circuit in FIG. 10 is about 5.5 nsec, for the signal transmission circuit shown in FIG. 13, the delay is shortened to 4.5 nsec.
As pointed out hereinbefore, in the aforementioned conventional example, when a number of inverters are connected as intermediate amplifiers so as to reduce the delay of the signal transmission, the power consumption is increased. This is a problem of contradiction. In addition, when the number of the inverters used as intermediate amplifiers is small, the power consumption is still high.Besides, when the number of the inverters used as intermediate amplifiers is increased, there is a limitation on the improvement of the delay of the signal transmission.
FIGS. 16 and 17 show specific circuit examples of other conventional signal transmission circuits designed for improving the aforementioned problems of a signal transmission circuit using inverter circuits.
In the signal transmission circuit shown in FIG. 16, driver circuit 60 and receiver circuit 61 are connected by a precharge circuit 62.
Driver circuit 60 comprises CMOS inverters 63, 64, driving p-type MOS transistors 65, 67, and driving n-type MOS transistors 66, 68.
Input terminal IN is connected to the input of inverter 63 and the gate of nMOS transistor 68; the output of inverter 63 is connected to the gate of pMOS transistor 65. The voltage applied on input terminal IN is applied as the gate voltage on the gate of pMOS transistor 65 and the gate of nMOS transistor 68, respectively.
The inverted input terminal N-IN is connected to the input of inverter 64 and the gate of nMOS transistor 66, and the output of inverter 64 is connected to the gate of pMOS transistor 67. The voltage applied on inverted input terminal N-IN is then applied as the gate voltage on the gate of pMOS transistor 67 and the gate of nMOS transistor 66 as the gate voltage.
The drain of nMOS transistor 66 is connected to the drain of pMOS transistor 65 to form a first transistor pair, while the drain of nMOS transistor 68 is connected to the drain of pMOS transistor 67 to form a second transistor pair.
On the other hand, receiver circuit 61 comprises nMOS transistors 71, 72, pMOS transistors 73-76, and CMOS inverters 77 and 78; nMOS transistors 71, 72 and pMOS transistors 73-76 are cross-coupled to each other.
The source of nMOS transistor 72 and the gate of pMOS transistor 74 are connected to the input side of CMOS inverter 77; the source of nMOS transistor 71 and the gate of pMOS transistor 75 are connected to the input side of CMOS inverter 78.
The precharge circuit 62 comprises nMOS transistors 69, 70. The source of nMOS transistor 69 is connected to the drain of nMOS transistor 65 of the driver circuit 60 and the drain of nMOS transistor 71 of the receiver circuit 61; the source of nMOS transistor 70 is connected to the drain of pMOS transistor 67 and the drain of nMOS transistor 72.
The gate of nMOS transistor 69 is connected to the gate and equalizer terminal EQ of nMOS transistor 70; the drain of nMOS transistor 69 is connected to the drain and V.sub.DD /2 terminal of nMOS transistor 70.
This signal transmission circuit is used in the signal circuit with a large wiring length of several cm, such as the address circuit, etc., in the LSI chip. As V.sub.DD /2 precharger functions, the signal is sent from the driver circuit 60 to receiver circuit 61 by precharge circuit 62; by means of the nMOS transistors 71, 72 of receiver circuit 61, the differential signal of the circuit threshold voltage V.sub.T h is derived. This differential signal is then converted to the CMOS voltage level by means of CMOS inverters 77, 78.
In this way, improvement can be realized with respect to the signal transmission delay, and the power consumption can be reduced.
FIG. 17 shows the circuit diagram of the intermediate amplifier circuit connected between the driver circuit and receiver circuit of the signal transmission circuit shown in FIG. 16.
In this intermediate amplifier circuit, the aforementioned differential signal is amplified by converting the differential signal to the CMOS signal, followed by reconverting the CMOS signal to the differential signal. The conversion is accomplished by a receiver circuit 79 which converts the differential signal of the input signal to a CMOS signal and a driver circuit 80 which converts the CMOS signal to the differential signal.
Receiver circuit 79 comprises input terminal IN, inverted input terminal N-IN, nMOS transistors 81, 82 for converting the differential signal to the CMOS signal, pMOS transistors 83-86, and CMOS inverters 87, 88 for amplifying the CMOS signal.
The nMOS transistor 81 and nMOS transistor 82 are connected to each other with their gates and drains connected in a crossed form; the pMOS transistor 84 and pMOS transistor 85 are connected to each other with their gates and sources connected in a crossed form.
CMOS inverters 87, 88 are connected to the gates of pMOS transistors 84, 85, respectively.
Driver circuit 80 comprises CMOS inverters 89, 90, pMOS transistors 91, 93 for converting the CMOS signal to the differential signal, nMOS transistors 92, 94, output terminal OUT and inverted output terminal N-OUT.
The outputs of CMOS inverters 89, 90 are connected to the gates of pMOS transistors 91, 93, the inputs of CMOS inverters 89, 90 are connected to the gate of nMOS transistor 94 and the gate of nMOS transistor 92.
However, as shown in FIGS. 10-13, for the conventional signal transmission circuit made of CMOS inverter circuits connected in series, as the chip size is increased, and the parasitic capacitance and parasitic resistance are increased, delay of the signal transmission time and increase in the power consumption cannot be ignored anymore.
As a replacement of the aforementioned signal transmission circuit, the signal transmission circuit shown in FIG. 16 has been proposed. Compared with the CMOS inverter circuit, the performance of this signal transmission circuit is improved, with the speed increased by about 10%, and power consumption decreased by about 30-40%.
However, in the signal transmission circuit shown in FIG. 16, for example, when the signal transmission distance within the LSI chip becomes longer than about 20 mm, it is impossible to make a simple serial connection of several intermediate amplifiers as in the signal transmission circuit shown in FIGS. 10-13. This is a disadvantage.
For the intermediate amplifier circuit for combining the driver circuit and the receiver circuit as shown in FIG. 17, as the differential signal has to be converted to a CMOS signal on the input side, while the CMOS signal has to be converted to a differential signal on the output side, the speed characteristic is naturally poorer than that of the conventional signal transmission circuit made of CMOS inverter circuits (FIGS. 11-13). This is a problem.
The purpose of this invention is to provide a type of signal transmission circuit wherein the signal transmission distance can be increased, and the signals can be transmitted at a high speed and with low power consumption. Another purpose of this invention is to provide a type of signal transmission circuit in which the signal is transmitted while being amplified by the positive feedback of an intermediate amplifier circuit having input/output shared terminals.